1. Field of the Invention
The present invention relates to a microcomputer, and particularly to a microcomputer taking data, which is transmitted in synchronization with a certain signal, into its internal storage device.
2. Description of the Background Art
For example, the following conventional techniques have been used for taking multiple bits of data, which are transmitted in synchronization with a certain signal, into a storage device such as an internal RAM (Random Access Memory) of a microcomputer.
A conventional interface circuit can hold a write control signal, an address control signal and data at rising and falling of a clock signal, and can reduce waiting times required for reading and writing (see, e.g., Japanese Patent Laying-Open No. 2003-067324).
A conventional microcomputer system can control external transfer of data to and from the microcomputer, and can also perform internal arithmetic processing of the microcomputer in a parallel manner (see, e.g., Japanese Patent Laying-Open No. 2001-209609).
A conventional data processing device can perform switching between single edge access and double edge access for use on one bus so that stream data can be efficiently transferred on the bus (see, e.g., Japanese Patent Laying-Open No. 2001-067310).
A conventional fast/slow interface circuit is controlled to switch a selector to an I/O circuit side only during a period for reading previously stored data from a memory, and to latch the data by a latch circuit, and the I/O circuit compares the previous data latch thus latched and the latch data so that a time required for access to a shared memory by the I/O circuit can be reduced (see, e.g., Japanese Patent Laying-Open No. 04-218857).
A conventional data transfer control device usually performs DMA (Direct Memory Access) processing in a burst operation mode, and can be automatically switched to a cycle steal operation mode when processing by a CPU (Central Processing Unit) is required. Thereby, the mode can be switched by an interrupt to the cycle steal mode when necessary (see, e.g., Japanese Patent Laying-Open No. 01-291354).
In a conventional bus arbitration device, it is possible to reduce an arbitration time for a bus master, which accesses a bus most frequently, and further, an arbitration between two bus masters is successively repeated so that the device can be easily applied to the case where three or more bus masters are employed (see, e.g., Japanese Patent Laying-Open No. 64-076254).
The following problem occurs when parallel data, which are input in synchronization with an external signal, are taken in by the DMA. First, a DMA start cycle may be disturbed due to bus contention between a CPU and the DMA. Since this causes a bottleneck in a fast operation when taking in external data, it is necessary to impose access limitation on the CPU. Second, definition of setup-time/hold-time may be required if DMA starts according to certain timing. This also causes a bottleneck in the fast operation.
Although the prior arts already described can partially overcome these problems, these problems can also be overcome by a technique other than the foregoing prior arts.